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| MH89792 E1 Line Interface Unit (LIU) Data Sheet Features * * * * * * * * * Complete primary rate 2048kbit/s E1line driver and receiver with clock recovery Meets ETSI requirements (ETSI ETS 300 011, NET 5) Onboard pulse transformers for transmit and receive No external crystal required for clock recovery Loss of signal indication Programmable polarity of extracted clock and receive data Compatible with MT8979, MT9079 and other E1 framers Single +5V operation Single In-Line (SIL) package occupying only 490mm2 area DS5712 Issue 4 March 2002 Ordering Information MH89792-1 MH89792-2 20 Pin SIL Package 20 Pin SIL Package * * -40C to 85C E1 Digital Loop Carrier (DLC) equipment Digital Cross-connect Systems (DCS) Description The Zarlink MH89792 is an E1 line interface unit (LIU) designed to meet the requirements of G.703 2048 kbit/s transmission. It incorporates all of the analog front-end components necessary to realize a complete, fully compliant short-haul E1 analog termination. These include, clock extractor, line driver/receiver, impedance matching resistors, and line transformers. No external components, such as crystals, inductors or transformers are required. An external clock reference is also not required. Two line impedance versions are available for 75 and 120 applications. See ordering information for details. Line Side Applications * * Primary rate ISDN network Interfaces Multiplexer equipment VDD VSS Equipment Side TxA TxB Line Driver Transmit Isolation Transformer 6dB Pad TLA TLB LOSP LOS RxP RxA RxB RxD E2o E2oP Clock Recovery Line Receiver Receive Isolation Transformer RLA RLB Figure 1 - Functional Block Diagram SEMICMF.019 1 MH89792 Data Sheet The MH89792 is compatible with the Zarlink MT8979 and MT9079 E1 digital framers, as well as other commercially available E1 framers. The MH89792 requires only a single +5 volt supply. The device is manufactured in a 20 pin Single In-Line (SIL) package. This package uses minimal board space area, making it optimal for high density E1 line card designs. Pin Connections E2o VDD RxA RxB VSS RxD RxP E2oP LOS LOSP NC RLA RLB TLA TLB NC NC NC TxA TxB 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Figure 2 - Pin Connections Pin Description Pin # 1 2 3 Name E2o VDD RxA Description 2048kHz Extracted clock (Output). This clock is extracted by the device from the received signal. It is used internally to clock in data received from RLA and RLB. Positive Power Supply (Input). +5V supply Receiver A (Output). The E1 signal received by the device at the RLA and RLB inputs is converted to return to zero (RZ) format and output at this pin. This output should be connected to the RxA or RxA of the E1 framer. Receiver B (Output). The E1 signal received by the device at the RLA and RLB inputs is converted to return to zero (RZ) format and output at this pin. This output should be connected to the RxB or RxB of the E1 framer. Negative Power supply (Input). Ground. Received Data (Output). This signal is the logically "OR" ed product of the RxA and RxB signals and should be connected to RxD of the MT8979. RxA/RxB Polarity Select (Input). A logic low applied to this pin will invert the outputs RxA and RxB (MT8979 application). A logic high should be applied if no inversion is required (MT9079 application). Clock Polarity Select (Input). A logic low selects E2o with a falling edge in the centre of RxD. A logic high selects E2o with a rising edge in the centre of RxD. Loss of Signal (Output). This pin goes low when 128 consecutive zeros are received on the RLA and RLB inputs. If a loss of signal condition is detected (LOS is low) then RxA and RxB are forced high if RxP is low. RxA and RxB are forced low if RxP is high. When 64 ones are received in 512 a bit period, the LOS condition is cleared (LOS is high). SEMICMF.019 4 RxB 5 6 7 VSS RxD RxP 8 9 E2oP LOS 2 Data Sheet Pin Description (continued) Pin # 10 11 12 13 14 15 16 17 18 19 20 Name LOSP NC RLA RLB TLA TLB NC NC NC TxA TxB Description MH89792 Loss of Signal Polarity Select (Input). A logic low applied to this pin will invert the polarity of the LOS output signal. No connection. This pin is not fitted. Received Line A (Input). The A wire or Tip Connection of the E1 receive line should be connected to this pin. Receive Line B (Input). The B wire or Ring connection of the E1 receive line should be connected to this pin. Transmit Line A(Output). The A wire or Tip connection of the E1 transmit line should be connected to this pin. Transmit Line B (Output). The B wire or Ring connection of the E1 transmit line should be connected to this pin. No Connection. This pin is not fitted. No Connection. This pin is not fitted. No Connection. This pin is not fitted. Transmit A (Input). This input should be connected to the TxA output of the framer. This signal must be a return to zero (RZ) form of the transmit data. Transmit B (Input). This input should be connected to the TxB output of the framer. This signal must be a return to zero (RZ) form of the transmit data. Functional Description The MH89792 is an E1 digital trunk interface, which when used with an MT8979 and MT9079 framer will conform to CCITT recommendation G.703 for PCM30 and I.431 for ISDN. The functions provided include line driver and receiver circuitry, clock recovery, loss of signal indication, as well as data and clock polarity selection. Bipolar Line Receiver The MH89792 receiver interfaces to the transmission line through an internal pulse transformer, which isolates the line side from the equipment side of the circuit. These two signals are combined by internal logic to form a new signal, which represents the received data, RxD. The signals RxA and RxB may be inverted where required by applying a logic low signal permanently to pin 7, (RxP). RxD will not be affected by use of this pin. The input impedance of the MH89792 receiver is nominally 120 when using the -1 variant (twisted pair applications), and nominally 75 when using the -2 variant (coaxial cable applications). The receiver input sensitivity exceeds G.703 requirements. Clock Extractor The MH89792 contains a clock extraction circuit which generates the E2o clock from the received data without the use of an external crystal or tunable inductor. The edge of the E2o extracted clock aligns approximately with the centre of the received data pulse and can be configured as either a rising or falling edge format by the use of pin 8 (E2oP). SEMICMF.019 3 MH89792 Data Sheet During a loss of signal condition, the E2o clock output will free-run at a nominal frequency of 2.048 kHz + 200 ppm. The input jitter tolerance of the MH89792 exceeds the minimum jitter tolerance as specified in CCITT I.431 and G.823 (see Figure 3). Loss of Signal The circuitry on the MH89792 is capable of detecting 128 continuous ZEROs received on RLA and RLB and indicating this condition as a logic low on pin 9, (LOS). If a loss of signal condition is detected (LOS is low) then RxA and RxB are forced high if RxP is low. RxA and RxB are forced low if RxP is high. LOS will not reset until 64 ONEs are received in a 512 bit period. The action of LOS may be inverted by applying a logic low to pin 10 (LOSP). A zero level is defined by voltage on the line, being less than 1.5V. UI 36.90 20.50 P E A K * T O * P E A K J I T T E R S 10.0 8.00 Note 1 2.50 Note 2 1.5 1.00 0.54 (SINUSOIDAL) 0.20 20 Hz 12 x 10-8 1 Hz 10 Hz 100 Hz JITTER FREQUENCY 2.4 kHz 1K 18 kHz 10 K 100 K Figure 3 - Typical Input Jitter Tolerance of MH89792 Note 1 - Typical jitter tolerance of receiver Note 2 - Minimum jitter tolerance specified by G.823 and I.431 4 SEMICMF.019 Data Sheet Bipolar Line Transmitter MH89792 The MH89792 transmitter interfaces to the transmission line through an internal pulse transformer which combines the TxA and TxB data into an AMI line coded signal. This is then passed through the 6dB pad prior to being applied to the line to meet return loss requirements. Functional timing for the transmitter is shown in Figure 4. The template for the transmitted pulse is shown in Figure 5. The nominal peak voltage of a mark is 3 volts for 120 twisted pair applications and 2.37 volts for 75 coax applications. The ratio of the amplitude of the positive and negative pulses of the transmit signals is between 0.95 and 1.05. No jitter is added by the transmitter circuitry. Transmitted Link Bit Cells TxA VIH or TxB VIL TLA or TLB VOH VOL Figure 4 - Functional Timing for Transmitter SEMICMF.019 5 MH89792 Percentage of Nominal Peak Voltage 120 110 100 194nS 90 80 244nS Data Sheet 269nS 50 10 0 -10 -20 219nS 488nS Nominal Pulse Figure 5 - Pulse Template (CCITT G.703) Applications Three typical 2.048 MHz E1/CEPT application are shown in Figures 6 and 7. Figure 6 shows the MH897921(120) with the MT8979 framer . Figure 7 shows the MH89792-1 (120) with the MT9079 advanced framer. Figure 8 shows the configuration of MH89792-2 (75). 6 SEMICMF.019 Data Sheet INT 19 3 12 17 8 DSTi XSt DSTo CSTi0 CSTo FRAMER CSTi1 RxD RxA RxB E2i C2i 21 13 C2 PLL MT9041 F0o PRI F0i 26 9 4 7 6 5 25 6 3 4 1 RxD RxA RxB E2o VSS 5 RxP 7 LOSP E2oP 10 8 TxA TxB MH89792-1 MT8979 16 1 2 9 19 20 LOS TxA TxB RLA LIU RLB 2 TLA TLB 14 MH89792 +5V To Network 15 12 From Network 13 Figure 6 - Connection Diagram for MH89792-1 with MT8979 and MT9041 SEMICMF.019 7 MH89792 + 5V + 5V R Data Sheet C 1 33 2 32 E8Ko 41 8-15 18-22 23 24 25 7 36 37 TAIS D0-D7 AC0-AC4 R/W CS DS IRQ S/P VSS C4i 26 14 C4 RxA RxB E2i F0i 31 30 29 27 6 3 4 1 RxD RxA RxB E2o VSS 5 LOSP 10 VDD RxP E2oP 2 7 8 FRAMER RESET DSTi DSTo MT9079 16 VDD TxMF TxA TxB 43 42 35 9 19 20 LOS TxA TxB MH89792-1 TLA TLB RLA LIU RLB 14 To Network 15 12 From Network 13 +5 V MT9041 PLL 9 F0o PRI 4 Figure 7 - Connection Diagram for MH89792-1 with MT9079 and MT9041 8 SEMICMF.019 Data Sheet +5V MH89792 MH89792-2 2 9 19 TxA 20 TxB LOS TLA TLB 14 Coaxial Cable 15 LIU 6 3 4 1 RxD RxA RxB E2o VSS 5 RxP 7 LOSP E2oP 10 8 RLA RLB 12 Coaxial Cable 13 Figure 8 - Configuration of MH89792-2 for 75 Coaxial Cable Line Protection Circuitry The MH89792 possesses minimal line protection capability. In order to meet relevant standards governing overvoltage/overcurrent stresses from lightening strikes and other surges, an external protection network is required. For information on suggested external line protection circuitry, please consult the factory. MH89792 12 RLA Line Protection 1 2 13 RLB LIU 14 TLA Line Protection 4 5 RJ48C 15 TLB Figure 9 - Protection Circuitry Requirement SEMICMF.019 9 MH89792 Absolute Maximum Ratings* Parameter 1 2 3 4 5 Supply Voltage with respect to VSS Voltage on any pin other than supplies Current at any pin other than supplies Storage Temperature Package Power Dissipation TST PD Symbol VDD Min VSS-0.3 -40 Max 6 VDD+0.3 40 85 1 Data Sheet Units V V mA C W * Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied. Recommended Operating Conditions - Voltages are with respect to ground (VSS) unless otherwise stated. Characteristics 1 2 Operating Temperature Supply Voltage Symbol TOP VDD Min 0 4.75 Typ 5.0 Max 70 5.25 Units C V DC Electrical Characteristics - Clocked operation over recommended temperature ranges and power supply voltages Parameters 1 2 3 4 5 Supply Current Input High Voltage Input Low Voltage Input Leakage Current Output High Voltage Output High Current 6 Output Low Voltage Output Low Current Sym IDD VIH VIL IIL VOH IOH VOL IOL 2.4 7 VSS 2 10 20 0.4 2.0 0.0 +1 Min Typ 10 Max 30 VDD 0.8 +10 VDD Units mA V V A V mA V mA VI = 0 to VDD IOH=7 mA @ VOH=2.4 V Source VOH=2.4 V IOL= 2 mA @ VOL=0.4 V Sink VOL=0.4 V Conditions Outputs Unloaded AC Electrical Characteristics - Timing Parameter Measurement Voltage Levels Characteristics 1 2 3 4 TTL Threshold Voltage CMOS Threshold Voltage Rise/Fall Threshold Voltage High Rise/Fall Threshold Voltage Low Sym VTT VCT VHM VLM Level 1.5 0.5VDD 2.0 0.7VDD 0.8 0.3VDD Units V V V V V V Conditions See Note 1 See Note 1 TTL CMOS TTL CMOS Notes: 1. Timing for output signals is based on the worst case result of the combination of TTL and CMOS threshold. 10 SEMICMF.019 Data Sheet AC Electrical Characteristics - Capacitance Characteristics 1 2 Input Pin Capacitance Output Pin Capacitance Sym C1 C0 Min Typ 10 10 MH89792 Max Units pF pF AC Electrical Characteristics - Line Transmitter(TST = 0 C to 70 C; VDD = 5.0 V +5%; VSS = 0V) Parameter 1 AMI Output Pulse Amplitudes MH89792-2 (75) MH89792-1(120) Transmitter Return Loss (for 75) 8 14 10 3 Transmitter Return Loss (for 120) 8 14 10 4 Isolation Voltage 1.5 14 18 15 dB dB dB KVrm s 13 18 15 dB dB dB Min 2.14 2.7 Typ 2.37 3 Max 2.6 3.3 Units V V Conditions Terminated with a 75 Load Terminated with a 120 Load Measured with transmitter in idle state 51 KHz to 102 KHz 102 KHz to 2.048 MHz 2.048 MHz to 3.072 MHz Measured with transmitter in idle state 51 KHz to 102 KHz 102 KHz to 2.048 MHz 2.048 MHz to 3.072 MHz 2 AC Electrical Characteristics - Line Receiver (TST = 0 C to 70 C; VDD = 5.0 V +5%; VSS = 0V) Parameter 1 Receiver Input Jitter Tolerance 0.2 1.5 2 Receiver Return Loss (for 75) 12 18 14 3 Receiver Return Loss (for 120) 12 18 14 4 5 Loss of Signal Threshold Receive Sensitivity 1.5 6 23 28 25 dB dB dB V dB 51 KHz to 102 KHz 102 KHz to 2.048 MHz 2.048 MHz to 3.072 MHz 23 27 20 dB dB dB 51 KHz to 102 KHz 102 KHz to 2.048 MHz 2.048 MHz to 3.072 MHz 1.7 11 UI UI 18 KHz - 100 KHz 2.4KHz Min Typ Max Units Conditions SEMICMF.019 11 MH89792 AC Electrical Characteristics - Link Timing (Figure 10) Characteristics 1 2 3 4 5 6 7 E2o Clock Period E2o Clock Width High or Low Receive Data Setup Time Receive Data Hold Time Receive Data Pulse Width Receive Data Fall Time Receive Data Rise Time Sym tPEC tWEC tRDS tRDH tRDW tRDF tRDR Min 439 195 98 49 195 244 293 20 30 Typ 488 244 Max 537 293 Units ns ns ns ns ns ns ns Data Sheet Conditions Note 1 Note 1 Note 1: The parameter tRDS and tRDH are related to device functionality Timing is over recommended operating temperature and power supply voltage ranges. Typical figures are at 25C and are for design aid only: not guaranteed and not subject to production testing. Received Link Bit Cells tWEC E2o VOH VOL tRDS Bit Cell tPEC tWEC tRDH RxA or RxB VOH VOL tRDR tRDW tRDF RxD VOH VOL Figure 10 - Receive Timing Link Note: 1. RxP is High and E2oP is High. 12 SEMICMF.019 Data Sheet ISOLATION BARRIER MH89792 1 PLL MH89792 LINE CONNECTORS FRAMER NETWORK SIDE 20 NOTES: X = Pin not fitted Separation across barrier > 2mm recommended. SYSTEM SIDE Figure 11 - Recommended Component Placement SEMICMF.019 13 For more information about all Zarlink products visit our Web Site at www.zarlink.com Information relating to products and services furnished herein by Zarlink Semiconductor Inc. trading as Zarlink Semiconductor or its subsidiaries (collectively "Zarlink") is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use. Neither the supply of such information or purchase of product or service conveys any license, either express or implied, under patents or other intellectual property rights owned by Zarlink or licensed from third parties by Zarlink, whatsoever. Purchasers of products are also hereby notified that the use of product in certain ways or in combination with Zarlink, or non-Zarlink furnished goods or services may infringe patents or other intellectual property rights owned by Zarlink. This publication is issued to provide information only and (unless agreed by Zarlink in writing) may not be used, applied or reproduced for any purpose nor form part of any order or contract nor to be regarded as a representation relating to the products or services concerned. The products, their specifications, services and other information appearing in this publication are subject to change by Zarlink without notice. No warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or service. Information concerning possible methods of use is provided as a guide only and does not constitute any guarantee that such methods of use will be satisfactory in a specific piece of equipment. It is the user's responsibility to fully determine the performance and suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. Manufacturing does not necessarily include testing of all functions or parameters. These products are not suitable for use in any medical products whose failure to perform may result in significant injury or death to the user. All products and materials are sold and services provided subject to Zarlink's conditions of sale which are available on request. Purchase of Zarlink's I2C components conveys a licence under the Philips I2C Patent rights to use these components in an I2C System, provided that the system conforms to the I2C Standard Specification as defined by Philips. Zarlink and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2002, Zarlink Semiconductor Inc. All Rights Reserved. TECHNICAL DOCUMENTATION - NOT FOR RESALE |
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